1. Field of the Invention
The present invention relates to a semiconductor package and a method for making the same, and more particularly to a semiconductor package having a redistribution layer and a method for making the same.
2. Description of the Related Art
There is a tendency of making smaller and lighter electrical products, so packages with higher intensity of pins and new packaging methods are developed. Those new packaging methods include: (1) Ball Grid Array (BGA), which uses solder balls to replace conventional pins, the solder balls being connected to a circuit board and disposed in array, (2) Flip Chip, which places an active surface of a chip downward to connect the chip and the substrate by Sn/Pb bumps; (3) Quad Flat Package (QFP). Currently, the most advanced packaging technique is redistribution layer (RDL). In conventional packaging technique, a solder joint must go through the center of a chip. However, the redistribution layer redistributes a solder joint to the periphery, two sides or any side of a chip; as a result, multi-chips can be stacked perpendicularly, crisscross, or side by side.
In the design and production of the conventional redistribution layer, the power signal and the ground signal are redistributed by long and thin traces of a single-layered layout. However, when high speed and high frequency signals are transferred, the long and thin traces of the single-layered layout cannot steadily control the characteristic impedance, so a noise of power is produced and the signal is rebounded, which is the main disadvantage.
Moreover, when the numbers and the intensity of the devices in an IC chip increase, the consumption of electricity increases. Although the redistribution layer redistributes the solder joint to the periphery, two sides or any side of the chip by the long and thin traces, it causes difficulty in heat dissipation, which increases the temperature of the chip and influences the characteristic and function of the chip. Finally, it leads to lower yield rate of the chip, which is another disadvantage.
Therefore, redistributing the solder joint of the signal input and output terminal by the conventional redistribution layer with long and thin traces has the disadvantages of high parasitic impedance, lack of voltage, and uncontrolled characteristic impedance. Moreover, the long and thin traces also increase thermal resistance, and the yield rate of the chip is reduced.